Permanent Position · Mid-level

FPGA Design Engineer

A specialized AI and silicon infrastructure company is seeking an engineer to bridge the gap between RTL and physical silicon. The role involves bringing physics-inspired ASIC designs to life on FPGA platforms for pre-silicon validation and early software development. The successful candidate will own the entire FPGA lifecycle, from platform selection and complex RTL implementation to lab debugging and software driver development. This position works closely with silicon, EDA, and research teams to build foundational hardware for critical AI infrastructure.

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Opportunity overview

Opportunity type
Permanent Position
Required seniority
Mid-level
Work location
Onsite
Location
United Kingdom
Start
ASAP
Duration
Permanent
Travel
—

Required role

System EngineerSystem Developer

Required platforms

Xilinx VivadoHAPSVCU118VPK180GitLab CIDocker

Required skills

FPGA PrototypingRTL DesignTiming ClosurePCIeSystemVerilogASIC ValidationHardware Abstraction LayerSignal Integrity

Required industry experience

SemiconductorsArtificial IntelligenceHardware Infrastructure

Responsibilities

  • Lead the selection, procurement, and bring-up of FPGA prototyping platforms for pre-silicon RTL validation.
  • Adapt and implement complex ASIC RTL onto FPGA targets, managing multi-clock-domain architectures and timing closure.
  • Integrate in-house designs with third-party and vendor IP within the AMD/Xilinx ecosystem.
  • Design and validate high-speed I/O interfaces with a primary focus on PCIe for server-based accelerators.
  • Build FPGA-based tester designs for silicon bring-up, device characterization, and automated test environments.
  • Develop hardware abstraction layers, register-map generation, and automated build flows using Python and C++.
  • Root-cause complex timing and functional issues using ILA, oscilloscopes, and logic analyzers.
  • Collaborate with cross-functional teams to validate silicon computing with noise.

Requirements

  • Proven industry experience taking FPGA designs from RTL through timing closure to validated hardware.
  • Expert-level SystemVerilog or VHDL for synthesis.
  • Deep proficiency in Xilinx Vivado including synthesis, place & route, and IP catalog.
  • Hands-on experience implementing and debugging PCIe, AXI/AHB, SPI, UART, and JTAG interfaces.
  • Strong Python skills for automation, test, and build tooling.
  • Demonstrated board-level bring-up and lab debugging skills on real hardware.
  • Ability to work independently in a fast-paced environment with ambiguous hardware/software problems.
  • Experience in ASIC prototyping or emulation environments.